Characteristics or performances of semiconductor memory devices are not equal to those of each other because conditions or circumstances for producing plural semiconductor memory devices in wafers, e.g., mass production, are not exactly and continuously kept. Particularly circumstance changes on fabrication process, i.e., PVT (Process, Voltage and Temperature), according to each memory chip are considered in order to revise the reference voltage VREF to target level.
FIG. 1 is a block diagram of a conventional internal voltage control device.
The conventional internal voltage control device includes a fuse ROM block 10, a decoder 20, an internal reference generator 30, a reference voltage selector 40 and a voltage comparator 50.
Each fuse ROM is provided with a fuse F, inverters IV1 to IV3 and a NMOS transistor N. The fuse F is connected between supply voltage and the NMOS transistor N. The NMOS transistor N connected between the fuse F and ground voltage receives a fuse enable signal FEN through a gate. The first and the second inverters IV1 and IV2 latch output of the fuse F. The third inverter IV3 inverting output of the latch outputs plural fuse signals FU<0> to FU<i−1>. Herein, i is a positive integer.
In addition, the decoder 20 decodes the plural fuse signals FU<0> to FU<i−1> and outputs plural switching signals SW<0> to SW<k−1>. Herein, k is positive integer. The internal reference generator 30 generates internal reference voltage PRE_VREF. The reference voltage selector 40 trims the internal reference voltage PRE_VREF according to the plural switching signals SW<0>-SW<k−1> and outputs reference voltage VREF.
The reference voltage selector 40 is provided with k number of NMOS transistors N0 to Nk−1, k+1 number of resisters RO to Rk connected in series. The plural NMOS transistors NO to Nk−1 respectively connected between the plural resisters RO to Rk and an output stage of the reference voltage VREF receive corresponding switching signal through gates. Accordingly the plural NMOS transistors are switched selectively.
The voltage comparator 50 is provided with an amplifier 51 and first and second resisters Ra to Rb. The amplifier 51 compares the reference voltage VREF and output of the resisters Ra to Rb, generating internal voltage VINT. The resisters Ra to Rb divide the internal voltage VINT through resister-division and output divided internal voltage VINT to the amplifier 51.
The conventional operation process of the internal voltage control device of FIG. 1 is described below.
When the fuse enable signal FEN is activated, the fuse ROMs are initialized. The NMOS transistor N turns on and node AA maintains low level during high pulse period of the fuse enable signal FEN. When the fuse enable signal FEN has low value, the node AA has high value through the fuse F. If the fuse F is cut electrically or physically, the node AA is disconnected with the supply voltage and the node AA has low value. As a result, fuse signals FU are controlled. Each fuse signal, i.e., the output of fuse ROM, is output at a logic high state if the fuse F is cut. On the contrary, a fuse signal having a logic low state is output in case that the fuse F is not cut.
Thereafter, the decoder 20 decodes the plural fuse signals FU<0> to FU<i−1> and outputs the plural switching signals SW<0> to SW<k−1>. The decoder 20 activates a corresponding signal of the plural switching signal SW<0> to SW<k−1> according to the fuse signals output high.
The internal reference generator 30 outputs an internal reference voltage PRE_VREF having a stably settled level regardless of an external voltage level and a chip temperature. However, the internal reference generator 30 cannot adjust a level of the internal reference voltage PRE_VREF in response to process change in fabrication. Accordingly each reference voltage PRE_VREF generated in each memory chip has a different level.
In order to trim the internal reference voltage PRE_VREF, the reference voltage selector 40 turns on one of the plural NMOS transistors N0 to Nk−1 according to the plural switching signals SW<0> to SW<k−1>, outputting a reference voltage VREF. Thereafter, the voltage comparator 50 outputs the internal voltage VINT having a predetermined voltage level based on the reference voltage VREF.
The internal voltage VINT is defined as follows.VINT=((Ra+Rb)/Rb)*VREF
The constant reference voltage VREF is required to output constant internal voltage VINT coping with process change. The reference voltage selector 40 switches the plural NMOS transistor N0 to Nk−1 selectively, generating constant level of reference voltage VREF.
In the event that level of the internal reference voltage PRE_VREF is high, a NMOS transistor Nk, herein k is a large number, turns on. In the event that level of the internal reference voltage PRE_VREF is low, a NMOS transistor Nk, herein k is a small number, turns on. Constant reference voltage VREF is output. For the above described operation, one of the k number switching signals SW<0> to SW<k−1> is activated by the operation of the fuse ROM block 10 and the decoder 20 after the reference voltage VREF or the internal voltage VINT is monitored in the manufactured chip.
The step for changing internal voltage through reliability or a worst condition test in a quality control process of conventional semiconductor memory chip is required. However, the level of the pre-programed internal voltage VINT is not changed in a conventional device controlling an internal voltage. Generating a stable internal voltage based on process changes in a semiconductor memory device is difficult.